Field of the Invention
The invention relates to a read-only memory cell device and a method for the production of a read-only memory cell device including a substrate formed of semiconductor material and having a main area, memory cells disposed in the vicinity of the main area in matrix form in columns and rows in a cell field, each memory cell having in each case at least one MOS transistor with a source region, a drain region, a channel region, a gate dielectric and a gate electrode, the MOS transistors of a column connected in series one after the other, each column connected to a bit line and the gate electrodes of the MOS transistors of a row connected to a word line.
Read-only memory cell devices of the generic type are disclosed, for example, in an article entitled "A 256 kbit ROM with Serial ROM Cell Structure", by R. Cuppens and L. H. M. Sevat, in IEEE Journal of Solid-State Circuits, Vol. SC-18, No. 3, June 1983, pages 340-344; and in an article entitled "High Density CMOS Read-Only Memories for a Handheld Electronics Language Translator", by S. Kamuro et al., in IEEE Transactions on Consumer Electronics, Vol. CE-27, No. 4, November 1981, pages 605 et seq. In those read-only memories a serially interconnected memory cell configuration having a NAND circuit configuration is used for the purpose of increasing the storage density per unit area. The formation of contact holes in the memory cell field can be avoided, as a result of which a very small ROM memory cell can be produced. However, it is necessary to accept a reduced access speed as compared with read-only memories which have a parallel-connected memory cell configuration with a NOR circuit configuration. However, for the purpose of storing considerable volumes of data in many of today's electronic systems, the primary feature is a maximum storage density. That is necessary in order to be able to accommodate a maximum number of memory cells per unit area with sufficiently low process costs to realize a corresponding cost advantage. In the case of the known ROM or OTP memory cells, it is possible to achieve a cell size of 5F.sup.2 with customary CMOS technologies using a serial circuit configuration of the memory cells in a NAND cell configuration. F denotes the smallest structure size that can be produced or resolved with the respective technology.
Moreover, further-developed read-only memory cell devices and methods for their production have been disclosed, for example, in German Patent DE 44 34 725 C1 and in German Published, Non-Prosecuted Patent Application DE 44 37 581 A1 having the same corporate assignee as the instant application. In those devices, memory cell transistors are constructed in a configuration which is vertical with respect to the main area of the silicon substrate. Such read-only memory cell devices, which are more advanced but are more complicated to produce, have a storage density of 2F.sup.2 cells.